The present disclosure relates to a digital pixel imager and, in particular, a digital pixel circuit that includes two bloom storage capacitors.
In legacy analog imagers, particularly infrared imagers, photo-current from a detector diode is integrated by a well capacitor coupled to the detector diode, and then once per video frame, the voltage or charge of each well capacitor is transferred to a down-stream analog-to-digital converter (ADC), where the voltage is converted to a binary value. Pixel sizes continue to shrink and the ratio of well capacitor to pixel area shrinks disproportionately more. Simultaneously, there is a demand by consumers for increased Signal-to-Noise Ratio (SNR) which can be realized by increasing effective well capacitance.
In-pixel ADC imagers are used to address this problem associated with decreasing pixel size. In particular, in-pixel ADC imaging improves photo-charge capacity for infrared imaging and other applications as the size of pixels continues to decrease. A good in-pixel ADC design can store nearly all of the available photo-charge from a detector diode and thus improve SNR to near theoretical limits. A common method of integration for in-pixel ADC circuits uses a quantizing analog front end circuit which accumulates charge over a relatively small capacitor, trips a threshold and is then reset. This pattern is repeated as more photo-current integrates.
An example of an in-pixel ADC circuit 100 is illustrated in FIG. 1. Charge from a photo-diode 110 is accumulated over an integration capacitor 115. As charge is accumulated across the integration capacitor 115 it is compared to a threshold voltage (Vref) by a comparator 120. When the voltage across the integration capacitor 115 (referred to as Vint herein) exceeds Vref, the circuit 100 is reset via a reset switch 130 that receives a control signal Reset. During a reset, a voltage equal to the difference between Vref and Vreset is subtracted from the integrating capacitor 115.
Control of the flow of current from the photo-diode 110 is controlled by an injection transistor 112. The gate of the injection transistor 112 is coupled to a bias voltage Vbias. The level of this voltage can be selected by the skilled artisan and is used, in part, to keep the photo-diode in reverse bias where the voltage at node 114 is lower than the diode supply voltage Vdiode. If the voltage at node 114 exceeds Vbias, current created in the photo-diode 110 is allowed to pass through the injection transistor 112 for accumulation by the integration capacitor 115.
Each reset event is accumulated (counted) with a digital counter circuit 135. At each frame, a “snapshot” of the contents of the digital counter 135 is copied into a register or memory and read out, line by line. This circuit 100 operates to exponentially increase the well capacity QINT of the integration capacitor 115 by a factor of 2N, where N is the size of the digital counter 135. Thus, by conserving the photo-charge relationship within a frame period, this type of read-out integrated circuit 100 may achieve improved signal-to-noise ratio.
After the integration time expires, any residual charge accumulated on the integration capacitor 115 can be read out by, for example, a single slope ADC or any other type of ADC. Such operations are known in the prior art.
The example in-pixel ADC circuit 100 illustrated in FIG. 1 is an asynchronous circuit. In asynchronous in-pixel ADCs, the comparator reset event occurs as soon as the voltage on the integrating capacitor 115 crosses the comparator threshold.